One of the limitations on the density scaling of integrated circuit (IC) patterns is the distance between two line ends. Fundamentally, this structure does not follow the same optical scaling as other features in critical circuit patterns (e.g., the critical dimension of a line). Therefore, the industry is always looking for better ways to bring line ends closer together. Starting around the 45 nm node, many IC manufacturers began a double patterning scheme where the lines were created using a first lithographic pattern, and then cut with structures resembling trenches or holes created during a second lithographic step.
In lithography, the creation of regular structures has a variety of applications. From a cost standpoint, the more densely that the structures are packed into a given area, the cheaper it is to fabricate the device. One of the key steps in creating a dense array of a patterned material is to cut an array of densely packed lines.
FIG. 1A depicts an array of densely packed lines 10, which constitute an existing topography 20 on a substrate 18. FIG. 1B then depicts a standard means for cutting the lines 10, namely a trench 12 is patterned in a photoresist 14 applied over the topography 20. FIG. 1C depicts the resulting array 60 of cut lines 10′. As we continue the path of scaling, however, the lithography of the printing of a trench pattern is reaching the limits of what can be achieved optically. This leads to a limit for the end-to-end spacing for abutting lines, and an overall decrease in the packing density of the circuits comprising these lines.
There is thus a need for means to allow smaller cut spaces to be created, and ideally, the means for making the cuts should be less expensive and require less critical lithography.